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thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. 1 / 2 7 s ecurity e thcv226 v-by-one? hs high-speed video data receiver general description thcv226 is designed to support video data transmission between the host and display. this chip can receive 32bit video data and 3bit control data via four differential pairs of v- by -one ? hs lanes. this chip in tqfp package supports the video data transmission up to 108 0p /10b/120hz. the maximum serial data rate is 3.4gbps/lane. features ? normal / hi gh-speed lvds output selectable ? 1.8v single power supply ? color depth selectable: 8/10 bits per colors ? crossing / distribution mode selectable ? monitoring signal function ? 1.8v lvttl i/o interface ? package: 128pin 0.4 mm -pitch tqfp (1 6 mm x 16mm) ? wide frequency range ? ac coupling for cml inputs ? cdr requires no external frequency reference ? supports spread spectrum clocking tolerance with u p to 30khz/ ? 0.5%(center spread) ? v- by -one ? hs standard compliant ? pll requires no external components ? power down / output enable mode block diagram cml deserializer cml deserializer cml deserializer cml deserializer l vds s e r ializer .. lvds ser ializer .. lvds s e r ializer .. lvds s e r ializer .. cdr pll controls deskew & formatter deskew & formatter cross switch vdd (1.8v) rx 0p rx 0n rx 1p rx 1n rx 2p rx 2n rx 3p rx 3n htpdn lockn betout dglock rla 0p/n rle 0p/n rlclk 0p/n .. rla 1p/n rle 1p/n rlcl k 1p/n .. rla 2p/n rle 2p/n rlclk 2p/n .. rla 3p/n rle 3p/n rlclk 3p/n .. color depth transmission mode setting power down output enable monitoring signal setting ? data transmission rate of cml input color depth normal speed lvds mode high - speed lvds mode 8bit 1.2 to 2.7gbps 1.2 to 2.36 gbps 10bit 1.6 to 3.4gbps 1.6 to 3.14gb ps ? clock frequency of lvds output color depth normal speed lvds mode high - speed lvds mode 8bit 40 to 90mhz 80 to 157mhz 10bit 40 to 85mhz 80 to 157mhz
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e pin configuration gnd rle 2p 1 iovdd 2 prbs 3 rs 4 map 5 reserved0 6 reserved1 7 reserved2 8 pdn 9 cvdd 1 0 pvdd 1 1 lvdd 1 2 gnd 1 3 rle 3p 1 4 rle 3n 1 5 rld 3p rld 3n 1 7 lvdd 1 8 gnd 1 9 rlclk 3p 20 rlclk 3n 21 rlc 3p 22 rlc 3n 23 lvdd 24 gnd 25 rlb 3p 26 rlb 3n 27 rla 3p 28 rla 3n 29 cvdd 30 gnd 31 lvdd 32 33 34 rle 2n rld 2p 35 36 rld 2n rlclk 2p 37 38 rlclk 2n gnd 39 40 lvdd rlc 2p 41 42 rlc 2n rlb 2p 43 44 rlb 2n gnd 45 46 lpvdd rla 2p 47 48 rla 2n rle 1p 49 50 rle 1n gnd 51 52 lpvdd rl d 1p 53 54 r ld 1n rlclk 1p 55 56 rlclk 1n gnd 57 58 lvdd rl c 1p 59 60 rl c 1n rlb 1p 61 62 rlb 1n rla 1p 63 64 rla 1n 66 65 gnd lvdd 68 67 rle 0p cvdd 70 69 rld 0p rle 0n 72 71 gnd rld 0n 74 73 rlclk 0p lvdd 76 75 rlc 0p rlclk 0n 78 77 gnd rlc 0n 80 79 rlb 0p lvdd 82 81 rla 0p rlb 0n 84 83 gnd rla 0n 86 85 cvdd lvdd 88 87 col gnd 90 89 mode0 o pf 92 91 mode2 mode1 94 93 reserved4 reserved3 96 95 gnd reserved5 100 99 98 97 iovdd oe reserved7 reserved6 104 103 102 101 cvdd d glock lockn htpdn 108 107 106 105 rx 0p rx 0n vvdd gnd 112 111 110 109 vvdd rx 1p rx 1n gnd 116 115 114 113 gnd rx 2p rx 2n gnd 120 119 118 117 gnd vvdd rx 3p rx 3n 124 123 122 121 mon_en bet_sel1 bet_sel0 cvdd 128 127 126 125 gnd betout bet_lat bet_en thcv226 tqfp 128pin 1 6 2/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e pin description pin name pin no type description rx 0n , rx 0p 107, 108 ci cml data i n p ut rx 1n , rx 1p 110, 111 ci cml data i n p ut rx 2n , rx 2p 114, 115 ci cml data i n p ut rx 3n , rx 3p 117, 118 ci cml data i n p ut rla 0n , rla 0p 83, 82 lo lvds data output rlb 0n , rlb 0p 81, 80 lo lvds data output rlc 0n , rlc 0p 77, 76 lo lvds data output rlclk 0n , rlclk 0p 75, 74 lo lvds data output rld 0n , rld 0p 71, 70 lo lvds data output rle 0n , rle 0p 69, 68 lo lvds data output rla 1n , rla 1p 64, 63 lo lvds data output rlb 1n , rlb 1p 6 2, 61 lo lvds data output rlc 1n , rlc 1p 60, 59 lo lvds data output rlclk 1n , rlclk 1p 5 6 , 5 5 lo lvds data output rld 1n , rld 1p 5 4 , 5 3 lo lvds data output rle 1n , rle 1p 50, 49 lo lvds data output rla 2n , rla 2p 48, 47 lo lvds data output rlb 2n , rlb 2p 44, 43 lo lvds data output rlc 2n , rlc 2p 42, 41 lo lvds data output rlclk 2n , rlclk 2p 38, 37 lo lvds data output rld 2n , rld 2p 36, 35 lo lvds data output rle 2n , rle 2p 34, 33 lo lvds data output rla 3n , rla 3p 29, 28 lo lvds data output rlb 3n , rlb 3p 27, 26 lo lvds data output rlc 3n , rlc 3p 23, 22 lo lvds data output rlclk 3n , rlclk 3p 21, 20 lo lvds data output rld 3n , rld 3p 17, 16 lo lvds data output rle 3n , rle 3p 15, 14 lo lvds data output dglock 10 1 bi connect all dglock pins in multiple - chip configuration. must be left open for single - chip configuration htpdn 10 2 od hot p lug d etect o utput must be connected to tx htpdn with a 10k ? pull - up resistor lockn 10 3 od lock d etect o utput must be connected to tx lockn with a 10k ? pull - up resistor col 88 i color depth select 1 : 10bit mode 0 : 8bit mode o pf 89 i output pattern at cdr fail condition (lockn= 1 ) 1 : lvds output low data 0 : lvds output hi - z data mode2,1,0 92,91,90 i input / output mode select oe 99 i lvds output enable 1 : normal operation 0 : output dis able bet_sel1,0 123, 122 i monitoring pin select 3/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e bet_en 125 i field - bet enable 1 : enable 0 : normal operation bet_lat 126 i latch select i n p ut under field bet operation 1 : latched result output 0 : reset latched result mon_en 124 i monitoring mode enable 1 : monitoring enable 0 : monitoring disable prbs 3 i must be tied to gnd or used for monitoring signal function, refer to table10. rs 4 i lvds swing level select 1 : normal swing (350mv) 0 : reduced swing (200mv) map 5 i lvds output format select 1 : jei d a format 0 : vesa format pdn 9 i power down 1 : normal operation 0 : power down operation beto ut 127 o field bet result output reserved 0 ,1,2,3,4,5 6, 7, 8, 93, 94, 95 i must be tied to gnd reserved 6,7 97, 98 o must be open cvdd 10, 30, 67, 86, 104, 121 pwr 1.8v power supply for logic block vvdd 106, 112, 119 pwr 1.8v power supply for v - by - one ? hs block lvdd 12, 18, 24, 32, 40, 5 8 , 65 , 73, 79, 85 pwr 1.8v power supply for lvds block pvdd 11 pwr 1.8v power supply for pll block lpvdd 46, 52 pwr 1.8v power supply for lvds analog block iovdd 2, 100, pwr 1.8v power supply for lvttl i/o buffer gnd 1, 13, 19, 25, 31, 39, 45, 5 1 , 57, 66, 72, 78, 84, 87, 96, 105, 109, 113, 116, 120, 128 gnd ground ci : cml input buffer , lo : lvds output buffer , bi : lvttl bi-directional buffer i : lvttl input buffer , o : lvttl output buffer , od : open drain buffer pwr : 1.8v power supply , gnd : ground 4/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e functional description functional overview with v- by -one ? hs s proprietary encoding scheme and cdr (clock and data recovery) architecture, thcv226 ena bles the transmission of 8 or 10-bit video data, 2-bit synchronizing control data of hsync, vsync, and data enable( de ), by a pair cable with minimal external components. thcv226 automatically extracts the clock from the incoming data streams and converts the serial data into video data with de being high or synchronizing control data with de being low, recognizing which type of serial data is being sent by the transmitter. also, thcv226 outputs the recovered data in the lvds data format. thcv226 can operate for a wide range of a serial bit rate from 1.2gbps to 3.4 gb ps. it is unnecessary to use any external frequency reference, such as a crystal oscillator. data enable requirement (de) there are some requirements for de signal as described in figure1 and figure2. if de=low, control data of same cycle and particular assigned data bit ctl except the first and last pixel are transmitted. otherwise video data is transmitted during de=high. control data fro m source device in de=high period is previous data of de transition. see figure2. the length of de being low and high must be at least 8 clock cycles long, as described in figure17 and table17. de must be toggled as high -> low -> high at regular interval. ctl bit transmission there is particular assigned data bit ctl which can be transmitt ed at blanking period except the first and the last pixel on de=low . r/g/b cont ctl vsync hsync de=1 , r/g/b, cont de=0 , ctl * except the 1 st and the last pixel other r/g/b, cont=low fixed. de=1 , hsync, vsync=fixed de=0 , hsync, vsync de thcv226 cont rol bit : hsync, vsync data bit : ctl* de data bit : r/g/b, cont 1 0 transmitter figure 1. ctl* are particular assigned bit s among r/g/b, cont that can carry arbitrary data during de= low period . 5/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e color depth mode function col operation m ode 1 10 - bit r/g/b data (4byte mode for v - by - one ? hs standard) 0 8 - bit r/g/b data (3byte mode for v - by - one ? hs standard) table 1. color depth mode select transmission mode select mode 2, 1, 0 col v - by - one hs lvds operation m ode 111 1 40 C 78.5 mhz 80 C 1 57 mhz hslvds / distribution mode 2 0 40 C 78.5 mhz 80 C 1 57 mhz 110 1 40 C 85mhz 40 C 85mhz normal lvds / di stribution mode 2 0 40 C 90mhz 40 C 90mhz 101 1 40 C 78.5 mhz 80 C 1 57 mhz hslvds / distribution mode 1 0 40 C 78.5 mhz 80 C 1 57 mhz 100 1 40 C 85mhz 40 C 85mhz normal lvds / distribution mode 1 0 40 C 90mhz 40 C 90mhz 011 1 40 C 78.5 mhz 80 C 1 57 mhz h slvds / crossing mode 0 40 C 78.5 mhz 80 C 1 57 mhz 010 1 40 C 85mhz 40 C 85mhz normal lvds / crossing mode 0 40 C 90mhz 40 C 90mhz 001 1 40 C 78.5 mhz 80 C 1 57 mhz hslvds mode 0 40 C 78.5 mhz 80 C 1 57 mhz 000 1 40 C 85mhz 40 C 85mhz normal lvds mode 0 40 C 90mhz 40 C 90mhz table 2. transmission mode select 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 d e v h 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 d e v h d e v h d e v h d e v h d e v h d e v h d e v h d e v h de=high active period de=low blanking period 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 v h 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 v h v h v h v h v h v h v h v h lo lo lo lo h i h i h i lo h i data : low fixed data : particular assigned bit ctl is transmitted except the first and l ast pixel of blanking period , o ther wise low fixed. tl yz p/n (lvds i n/p ut) tl c p/n (lvds i n/p ut) tlclk p/n (lvds i n/p ut) r l yz p/n (lvds out put) rl c p/ n (lvds out put) rlclk p/n (lvds out put) lvds input of source device thcv226 lvds transmitter output figure 2. timing diagram of data and s ynchronizing s ignal s y=a,b,d,e z=0,1,2,3 6/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e power down mode pdn operation 1 normal operation 0 power d own operation table 3. power down mode rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p rx 0n/p rx 1n/p rx 2n/p rx 3n/p rly 0n/p rly 1n/p rly 2n/p rly 3n/p mode2,1,0 = 111 mode2,1,0 = 110 mode2,1,0 = 101 mode2,1,0 = 100 mode2,1,0 = 011 mode2,1,0 = 010 mode2,1,0 = 001 mode2,1,0 = 000 hslvds / distribution mode normal lvds / distribution mode hslvds mode normal lvds mode figure 3. transmission mode select diagram y=a,b,c,clk,d,e 7/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e hot-plug and lock detect function htpdn and lockn are both open drain outputs from thcv226. pull-up resistors must be placed at v- by -one ? hs transmitter side. see figure.4 and 5 . if thcv226 is not active (power down mode (pdn=0) or powered off), htpdn is open. otherwise, htpdn is pulled down by thcv226. htpdn at v- by -one ? hs transmitter side is high when thcv226 is not active or the receiver board is not connected. then v- by -one ? hs transmitter side enters into the power down mode. when htpdn transits from high to low, v- by -one ? hs transmitter starts up and transmits training pattern for link training. lockn indicates whether thcv226 is in cdr state or not. if thcv226 is in the cdr unlock state, lockn is open. otherwise (in the cdr lock state), it is pulled down by thcv226. v- by -one ? hs transmitter side keeps transmitting training pattern until lockn transition to low. after training is done, thcv226 sinks current, and lockn turns to low. then v- by -one ? hs transmitter side starts transmitting normal video pattern. thcv226 htpdn lockn transmitter htpdn lockn (tx side) (tx side) figure 4. htpdn and lockn s cheme transmitter htpdn lockn dglock pdn vdd thcv226 htpdn lockn transmitter htpdn lockn (tx side) figure 5. ht pdn and lockn s cheme without htpdn co n nection transmitter h tpdn lockn dglock pdn vdd 8/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e multiple-chip configuration in order to reduce the number of cables needed for htpdn and lockn in multiple-chip configuration, thcv226 is equipped with the dglock pin. when all the dglock pins are connected as in figure 6 , the connected rx chips can share the cdr lock status via dglock, making all the rx chips in the same operation status. field bet operation in order to help to debug high-speed serial links of cml lines, thcv226 has an operation mode acted as the bit error tester (field bet). in the field bet mode, the on-chip pattern generator on v- by -one ? hs transmitter side is enabled and generates a test pattern. thcv217, which is an example of tx device, has this function mode. in this mode, thcv217 internally generates the test pattern, encodes the data according to the 8b10b protocol, scrambles, and then serializes onto the cml high-speed lines. thcv226 receives the data stream and checks whether the sampled data has bit error. field bet mode of thcv226 is activated by setting bet_en=1. as for thcv226, when the internal test pattern check circuit is enabled, the pattern check result can be monitored at the betout pin. the betout pin goes low whenever bit errors occur and stays high when there is no bit error. please refer to figure 7 and figure 8. table 5 shows possible combination of tx and rx for normal and field bet operation. betout result / %lwhuururffxuuhg + 1rhuuru 7deoh field bet result thcv226 htpdn lockn transmitter htpdn lockn (tx side) (tx side) figure 6. usag e of dglock in m ultiple - rx c onfiguration transmitter htpdn lockn dglock thcv226 htpdn lockn transmitter htpdn lockn transmitter htpdn lockn dglock ( r x side) pdn pdn vdd 9/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e thcv 217 thcv226 condition bet bet_en bet_lat bet_sel 1 bet_sel 0 operation output latch s elect 0 0 0 - - normal o peration - 1 - - forbidden - 0 1 - - - forbidden - 1 0 - - - forbi dden - 1 1 0 0 0 field bet operation (lane0) reset latched result 1 latched result 0 0 1 field bet operation (lane1 ) reset latched result 1 latched result 0 1 0 field bet operation (lane2) reset latched result 1 latched result 0 1 1 field bet operation (lane3) reset latched result 1 latched result table 5. field bet operation lvds reduced swing output function rs pin controls lvds output swing level. rs output swing l evel 5hgxfhg6zlqj / hyhop9w\slfdo 1rupdo6zlqj/ hyhop9w\slfdo 7deoh lvds output level select test pattern generator test pattern checker bet_en bet_lat clkin bet = 1 betout test point fo r field bet figure 7. field bet configuration thcv21 7 thcv226 rxy n / p y =0,1,2,3 thcv219 (bet) bit error bit error betout bet_lat reset latched result latched result figure 8. relationship between b it e rror and betout field bet operation normal operation 10/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e lvds output enable function by setting the oe and opf pins, the following output enable function can be selected. in output disable condition, all the outputs take low fixed data or high-z except for htpdn, lockn and dglock. lockn oe opf lvds outputs status o utput condition + 2xwsxw(qdeoh /rz)l[hg'dwd +l = 2xwsxw'lvdeoh /rz)l[hg'dwd +l = / 2xwsxw(qdeoh 1rupdo'dwd 2xwsxw'lvdeoh /rz)l[hg'dwd +l = 7deoh lvds output enable function lvds data mapping lvds data (video data, control data, de) are mapped as figure 9. rlc[6] is special bit for de (data enable). rlc[5:4] are for control data bits, and the other bits are for video data. also there are special assigned bits, ctl transmitted under de=0 condition. the number of lvds channels depends on color depth mode, col. rld[6] is not available at col=0, 8-bit color depth mode. vdiff = 0 rla zp/n (rlclk zp ) C (rlclk zn ) figure 9. lvds output switching timing diagram rlb zp/n rlc zp/n rld zp/n rle zp/n rlaz [0 ] trcop p revious cycle current cycle next cycle z = 0,1,2,3 rlaz [1 ] rlaz [2 ] rlaz [3 ] rlaz [4 ] rlaz [5 ] rla z[6 ] rla z[0 ] rla z[1 ] rla z[2 ] rla z[3 ] rla z[4 ] rla z[5 ] rla z[6 ] rla z[0 ] rla z[1 ] rl bz[0 ] rl bz[1 ] rl bz[2 ] rl bz[3 ] rl bz[4 ] rl bz[5 ] rl bz[6 ] rl bz[0 ] rl bz[1 ] rl bz[2 ] rl bz[3 ] rl bz[4 ] rl b z[5 ] rl bz[6 ] rl bz[0 ] rl bz[1 ] rl cz[0 ] rl cz[1 ] rl cz[2 ] rl cz[3 ] rl cz[4 ] (h) rl cz[5 ] (v) rl cz[6 ] (de) rl cz[0 ] rl cz[1 ] rl cz[2 ] rl cz[3 ] rl cz[4 ] (h) rl cz[5 ] (v) rl cz[6 ] (de) rl cz[0 ] rl cz[1 ] rl dz[0 ] rl dz[1 ] rl dz[2 ] rl dz[3 ] rl dz[4 ] rl dz[5 ] rl dz[6 ] rl dz[0 ] rl dz[1 ] rl dz[2 ] rl dz[3 ] rl dz[4 ] rl dz[5 ] rl dz[6 ] rl dz[0 ] rl dz[1 ] rl ez[0 ] rl ez[1 ] rl ez[2 ] rl ez[3 ] rl ez[4 ] rl ez[5 ] rl ez[6 ] rl ez[0 ] rl ez[1 ] rl ez[2 ] rl ez[3 ] rl ez[4 ] rl ez[5 ] rl ez[6 ] rl ez[0 ] rl ez[1 ] data enable control data b it s data width 32 24 11/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e thcv226 output col comment 0 (8bit) 1 (10bit) rlaz[0] r[2] r[4] data bit rlaz[1] r[3] r[5] data bi t rlaz[2] r[4] r[6] data bit rlaz[3] r[5] r[7] data bit rlaz[4] r[6] r[8] data bit rlaz[5] r[7] r[9] data bit rlaz[6] g[2] g[4] data bit rlbz[0] g[3] g[5] data bit rlbz[1] g[4] g[6] data bit rlbz[2] g[5] g[7] data bit rlbz[3] g[6] g[8] data bit r lbz[4] g[7] g[9] data bit rlbz[5] b[2]*2 b[4]*2 data bit rlbz[6] b[3]*2 b[5]*2 data bit rlcz[0] b[4]*2 b[6]*2 data bit rlcz[1] b[5]*2 b[7]*2 data bit rlcz[2] b[6]*2 b[8]*2 data bit rlcz[3] b[7]*2 b[9]*2 data bit rlcz[4] hsync hsync control bit rlcz [5] vsync vsync control bit rlcz[6] de de data enable*2 rldz[0] r[0] r[2] data bit rldz[1] r[1] r[3] data bit rldz[2] g[0] g[2] data bit rldz[3] g[1] g[3] data bit rldz[4] b[0]*2 b[2]*2 data bit rldz[5] b[1]*2 b[3]*2 data bit rldz[6] n/a*1 cont[1]* 2*3 data bit rlez[0] channel power down r[0]*2 data bit rlez[1] r[1]*2 data bit rlez[2] g[0]*2 data bit rlez[3] g[1]*2 data bit rlez[4] b[0]*2 data bit rlez[5] b[1]*2 data bit rlez[6] cont[2]*2*3 data bit table 8. lvds data mapping table for jeid a format (map=1) *1 n/a : not available. thcv226 outputs rldz[6]=0 *2 ctl bits, which are carried during de=0 expect the 1st and the last pixel. *3 3d flags defined in the v- by -one ? hs standard are assigned to the following bits. v- by -one ? hs standard packer/unpacker d[24](3dlr) ? lvds rlez[6]. v- by -one ? hs standard packer/unpacker d[25](3den) ? lvds rldz[6]. ( z=0,1,2,3) 12/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e thcv226 output col comment 0 (8bit) 1 (10bit) rlaz[0] r[0] r[0]*2 data bit rlaz[1] r[1] r[1]*2 data bit rlaz[2] r[2] r[2 ] data bit rlaz[3] r[3] r[3] data bit rlaz[4] r[4] r[4] data bit rlaz[5] r[5] r[5] data bit rlaz[6] g[0] g[0]*2 data bit rlbz[0] g[1] g[1]*2 data bit rlbz[1] g[2] g[2] data bit rlbz[2] g[3] g[3] data bit rlbz[3] g[4] g[4] data bit rlbz[4] g[5] g[5 ] data bit rlbz[5] b[0]*2 b[0]*2 data bit rlbz[6] b[1]*2 b[1]*2 data bit rlcz[0] b[2]*2 b[2]*2 data bit rlcz[1] b[3]*2 b[3]*2 data bit rlcz[2] b[4]*2 b[4]*2 data bit rlcz[3] b[5]*2 b[5]*2 data bit rlcz[4] hsync hsync control bit rlcz[5] vsync vsync control bit rlcz[6] de de data enable*2 rldz[0] r[6] r[6] data bit rldz[1] r[7] r[7] data bit rldz[2] g[6] g[6] data bit rldz[3] g[7] g[7] data bit rldz[4] b[6]*2 b[6]*2 data bit rldz[5] b[7]*2 b[7]*2 data bit rldz[6] n/a*1 cont[1]*2*3 data bit r lez[0] channel power down r[8] data bit rlez[1] r[9] data bit rlez[2] g[8] data bit rlez[3] g[9] data bit rlez[4] b[8] *2 data bit rlez[5] b[9] *2 data bit rlez[6] cont[2]*2*3 data bit table 9. lvds data mapping table for vesa format (map=0) *1 n/a : not available. thcv226 outputs rldz[6]=0 *2 ctl bits, which are carried during de=0 expect the 1st and the last pixel. *3 3d flags defined in the v- by -one ? hs standard are assigned to the following bits. v- by -one ? hs standard packer/unpacker d[24](3dlr) ? lvds rlez[6]. v- by -one ? hs standard packer/unpacker d[25](3den) ? lvds rldz[6]. ( z=0,1,2,3) 13/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e monitoring signal function the recovered hsync, vsync, de or clk from v- by -one ? hs signals can be monitored by monitoring signal function. the monitoring lane out of four high-speed data lane is selectable. this function is used for debugging purpose and set by five pins, mon_en, bet_sel1, bet_sel0, bet_lat and prbs. the monitoring signal is outputted from betout pin as 1.8v lvttl signal. all signals operate as normal mode except these setting pins and monitoring output pin when monitoring signal function is enabled. see the table below. pin option monitoring output description function lane selection signal selection mon_en bet_sel1 bet_sel0 bet_lat prbs betout %(7b6(/ %(7b6(/ %(7b/$7 %(7287 1rupdoprgh '( 0rqlwrulqj6ljqdo0rghwr & khfn/dqh +6<1& 96<1& &/. '( 0rqlwrulqj6ljqdo0rghwr & khfn/dqh +6<1& 96<1& & /. '( 0rqlwrulqj6ljqdo0rghwr & khfn/dqh +6<1& 96<1& &/. '( 0rqlwrulqj6ljqdo0rghwr & khfn/dqh +6<1& 96<1& &/. 7deoh monitoring signal function 14/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e absolute maximum ratings parame ter m in t yp m ax u nit supply voltage (vvdd,lvdd ,lpvdd ,pvdd,cvdd,iovdd) - 0.3 - 2.1 v cmos/ttl i n p ut voltage - 0.3 - io vdd+0.3 v cmos/ttl output voltage - 0.3 - iovdd+0.3 v open drain input voltage - 0.3 - 3.6 v cml receiver input voltage - 0.3 - vvdd+0.3 v lvds transmitter output voltage - 0.3 - lvdd+0.3 v output cur rent - 50 - 50 ma storage temperature - 55 - 125 c junction temperature - - 125 c reflow peak temperature/time - - 260/10 c/sec maximum power dissipation @+25deg - - 2. 5 w table 11. absolute maximum ratings recommended operating conditions symbol parameter m in t yp m ax u nit vdd supply voltage (vvdd,lvdd, lpvdd, pvdd,cvdd,iovdd) 1.62 1.80 1.9 8 v ta operating temperature - 40 - 85 c table 12. recommended operating condition electrical specifications symbol parameter condition m in t yp m ax u nit vih high level i n p ut voltage 0.65 vdd - vdd+0.3 v vil low level i n p ut voltage - 0.3 - 0.35 vdd v voh high level output voltage ( io type : o ) *1 ioh = - 2 ma vdd - 0.2 - vdd v vol low level output voltage ( io type : o ,od ) *1 iol = 2 ma gnd - 0.2 v low level output voltage ( io type : bi ) *1 iol = 160ua gnd - 0.2 v iozh output leak current high in hi - z state - 10 - 10 ua iozl output leak current low in hi - z state - 10 - 10 ua iih high level i n p ut leakage c urrent - 10 - 10 ua iil low level i n p ut leakage c urrent - 10 - 10 ua table 13. electrical specifications *1 io type : o = betout , reserved6,7 od = htpdn, lockn bi = dglock 15/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e symbol parameter condition m in t yp m ax u nit vrth cml differential i n p ut high threshold - - 50 mv vrtl cml differential i n p ut low threshold - 50 - - mv irih cml i n p ut high leak current pdn= 0 , rx zp /n = vdd - 10 - 10 ua iril cml i n p ut low leak current pdn=0 rx zp/n = gnd - 10 - 10 ua irrih cml i n p ut high current rx zp/n = vdd - - 2 m a irril cml i n p ut low current rx zp/n = gnd - 6 - - ma rrin cml differential i n p ut resistance 80 100 120 ? ? table 14. electrical specifications ( z=0,1,2,3 ) symbol parameter condition m in t yp m ax unit 952' /9'6'liihuhqwldo0rgh2xwsxw 9rowdjh 5/ ? ? ?? ? ? ? ? ? ???? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? vdd - 2 0 - 2 0 ua table 15. electrical specifications ( y=a,b,c,clk,d,e / z=0,1,2,3 ) supply current symbol parameter conditions m in t yp (*1) m ax u nit irccw power supply current (worst case pattern) 10bit mode mode2,1,0=111 - 450 515 ma mode2,1,0=001 360 415 mode2,1,0=000 420 475 mode2,1,0=100 295 335 power supply current (gray scale pattern) 10bit mode mode2,1,0=111 370 440 mode2,1,0=001 300 355 mode2,1,0=000 345 405 mode2,1,0=100 245 285 irccs power down supply current pdn = 0 - - 1 m a table 16. supply current *1 : vdd=1.8v, room temperature 16/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e switching characteristics symbol parameter condition m in t yp m ax unit trbit unit interval (ui) col = 0 370 tr co p/30 83 3 ps col = 1 294 tr co p/40 625 ps trisk cml lane0/1/2/3 i n p ut inter pair skew margin col = 0 - 30 - 30 ui col = 1 - 40 - 40 ui tr ijt cml lane0/1/2/3 input jitter margin col = 0 - - 15 ui col = 1 - - 20 ui tr cop clock out period 6.37 - 25 ns trlv t lvds differential output transition time - 0.6 1.5 ns trop1 lvds output data position0 hslvds mode ( trcop= 6.37ns C 8.33 ns ) - 0.2 0 - 0.2 0 ns trop0 lvds output data position1 trcop/7 - 0. 20 trcop/7 trcop/7 +0.2 0 ns trop6 lvds output data position2 2 trcop/7 - 0.2 0 2trcop/7 2trcop/7 +0.2 0 ns trop5 lvds output data position3 3trcop/7 - 0.2 0 3trcop/7 3trcop/7 +0.2 0 ns trop4 lvds output data position4 4trcop/7 - 0.2 0 4trcop/7 4trcop/7 +0.2 0 ns trop3 lvds output data position5 5trcop/7 - 0.2 0 5trcop/7 5t rcop/7 +0.2 0 ns trop2 lvds output data position6 6trcop/7 - 0.2 0 6trcop/7 6trcop/7 +0.2 0 ns trop1 lvds output data position0 normal lvds mode (trcop= 11.1ns - 16.6ns) - 0.25 - 0.25 ns trop0 lvds output data position1 trcop/7 - 0.25 trcop/7 trcop/7 +0.25 ns trop6 lvds output data position2 2trcop/7 - 0.25 2trcop/7 2trcop/7 +0.25 ns trop5 lvds output data position3 3trcop/7 - 0.25 3trcop/7 3trcop/7 +0.25 ns trop4 lvds output data position4 4trcop/7 - 0.25 4trcop/7 4trcop/7 +0.25 ns trop3 lvds output da ta position5 5trcop/7 - 0.25 5trcop/7 5trcop/7 +0.25 ns trop2 lvds output data position6 6trcop/7 - 0.25 6trcop/7 6trcop/7 +0.25 ns trosk link0/1/2/3 lvds output clock skew - 250 - 250 ps tr dc input data to output data delay mode0 = 0 col = 0 (17+27/3 0) trcop+4 .5 - (17+27/3 0) trcop+13 .5 n s mode0 = 1 col = 0 (34+2 4 /3 0) trcop+5 .0 - (34+2 4 /3 0) trcop+15 .5 17/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e mode0 = 0 col = 1 (17+7/4 0) trcop+4 .5 - (17+7/4 0) trcop+13 .5 ns mode0 = 1 col = 1 (33+14 /4 0) trcop+5 .0 - (33+14 /4 0) trcop+15 .5 trpd powe r on to pdn high delay 0 - - ns trhpd0 pdn high to htpdn low delay - - 1 us trhpd1 pdn low to htpdn high delay - - 1 us trpll0 training pattern input to lockn low delay - - 10 ms trpll1 pdn low to lockn high delay - - 10 us trpll2 lockn low to lv ds clk lock time - - 10 ms trlck0 lockn low to lvds output delay - - 1 ms trlck1 lockn high to lvds output high - z /low delay - - 1 ms trdlh dglock high to lockn low 0 - - ns trdll dglock low to lockn high 0 - - ns trdeh de=1 duration mode0 = 0 8tr cop - - ns mode0 = 1 16trcop - - ns trdel de=0 duration mode0 = 0 8trcop - - ns mode0 = 1 16trcop - - ns table 17. switching characteristics 18/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e ac timing diagram and test circuit (tx side) (tx side) cml transmitter cml receiver (thcv226) vterm = 1.3v(typ) 50 ? 50 ? 50 ? figure 10 . cml buffer scheme 50 ? tx zp tx zn rx zp rx zn zo=50 ? z=0,1,2,3 c=75 20 0n f c=75 20 0n f vdiff = (rx 0p ) C (rx 0n ) vdiff = (rx 1p ) C (rx 1n ) vdiff = (rx 2p ) C (rx 2n ) vdiff = (rx 3p ) C (rx 3n ) - trisk + trisk vdiff = 0 vdiff = 0 vdiff = 0 vdiff = 0 figure 1 1 . cml i n p ut timing diagram + trisk tri jt trbit (1 ui ) cl= 5pf r l=100 ? 20% 8 0% vdiff = (rly zp ) C (rly zn ) y = a,b,c,clk,d,e z=0,1,2,3 rly zp rly zn figure 1 2 . lvds output switching timing diagram and test circuit trlvt trlvt 19/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e trop1 rlyz5 vdiff = 0 trco p vdiff = (rly zp ) C (rly zn ) vdiff = (rlc lk zp ) C (rlclk zn ) figure 1 3 . lvds output switching timing diagram y = a,b,c,d,e z = 0,1,2,3 rl yz4 rl yz3 rl yz2 rl yz1 rl yz0 rl yz6 rl yz5 rl yz4 rl yz3 rl yz2 rl yz1 rl yz0 trop0 trop6 trop5 trop4 trop3 trop2 vdiff = 0 vdiff = (rlclk zp ) C (rlclk zn ) figure 1 4 . lvds output switching timing diagram v diff = 0 vdiff = (rlclk zp ) C (rlclk zn ) trosk z = 0,1,2,3 vdiff = 0 vdiff = (rlclk zp ) C (rlclk zn ) figure 1 5 . v - by - one ? hs i n p ut to lvds output latency vdiff = (rx zp ) C (rx zn ) z = 0,1,2,3 p ix el 1st bit trdc current cycle p revious cycle 20/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e vdd pdn htpdn rx zp/n lockn rlclk zp/n opf =0 rly zp/n opf =0 trpd trhpd0 trpll0 trpll2 trhpd1 trpll1 trlck1 training pattern normal pattern invalid pattern valid pattern vdd pdn htpdn rx z/p/n lockn rlclk zp/n opf =1 rly zp/n opf =1 trpll0 trpll2 trhpd1 trpll1 trlck1 train ing pattern normal pattern invalid pattern valid pattern invalid pattern low pattern low patt ern figure 1 6 . thcv226 lock/unlock sequence hi - z hi - z hi - z hi - z y = a,b,c,d,e z = 0,1,2,3 trpd trhpd0 invalid pattern invalid clock invalid clock invalid clock invalid clock trlck0 trlck0 invalid pattern invalid clock invalid pattern invalid clock hi - z hi - z hi - z hi - z training pattern training pattern normal pattern training pattern training pattern normal patte rn invalid pattern invalid clock valid pattern valid pattern dglock trdlh trdll dglock trdlh trdll vdiff = (rlclk zp ) - (rlc lk zn ) de de de de de de vdiff = (rlc zp ) - (rlc zn ) t r deh t r del figure 1 7 . de period r equirement z = 0,1,2,3 21/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e note 1) lvds output pin connection in case that the lvds rx of destination device is equipped with pull-up resistors connected to higher than thcv226s vdd voltage, this can cause violation of absolute maximum ratings to thcv226. this phenomenon may be happened at power-on phase and hi-z state of the whole system including lvds rx device. one solution for this problem is power-down control for lvds rx device during no lvds input or hi-z state period, if its pull-up resistors can be cut off at power-down state. another solution is to set thcv226s opf option pin to vdd. this setting provides low fixed data output mode at pdn=1, not hi-z state mode. 2) cable connection and disconnection do not connect and disconnect the lvds and cml cables, when the power is supplied to the system. 3) gnd c onnection connect the each gnd of the pcb which transmitter and receiver. it is better for emi reduction to place gnd cables as close to lvds and cml cables as possible. 4) multi-dr op connect multi-drop connect is not recommended. lvdd(1.8v) hvdd(3.3v) 1.8v thin transistor lvds buffer lvds receiver ! thcv226 lvds rx lvds rx 22/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e 5 ) multiple counterpart u se multiple counterpart use such as the following system is not recommended. if it is not avoidable, please check whether trisk and trijt spec of thcv226 can be kept or not. furthermore, please contact to mspsupport@thine.co.jp (for fae mailing list) 6 ) multiple device connection htpdn and lockn signals are supposed to be connected proper ly for their purpose like the following figure. htpdn should be from just one thcv226 to multiple tx devices because its purpose is only ignition of all tx devices. lockn should be connected so as to indicate that cdr status of all rx devices becomes ready to receive normal operation data. lockn of tx side can be simply split to multiple tx devices. thcv226 s dglock is appropriate for multiple rx use. also possible time difference of internal processing time (thcv226 trdc ) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple thcv226s, which may have internal fifo. v - by - one ? hs tx clkout data v - by - one ? hs tx clkout data tx0n/p tx1n/p tx2n/p tx3n/p thcv226 ic ! 23/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e source device htpdn lockn thcv 226 htpdn lockn dglock thcv 226 htpdn lockn dglock destination device time diff . comes up clkin clkout.1 internal processing time trdc fifo fifo clkout.2 clkout.3 clkout.4 clkout.1 clkout.2 clkout.3 clkout.4 source device 1 htpdn lockn thcv 226 htpdn lockn dglock thcv 226 htpdn lockn dglock destination device ex. synchronized time diff . comes up clkin.1 clkin.2 clkout.1 internal processing time trdc fifo fifo source device 2 lockn clkout.2 clkout.3 clkout.4 clkout.1 clkout.2 clkout.3 clkout.4 htpdn 24/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e package 1.20 max 1 32 64 33 97 65 98 128 unit : mm 0.25 typ 16.0 0 14.0 0 16.0 0 14.0 0 0.40 + 0.05 0.18 +0.05 1.00 + 0.05 0.45 0.75 1.00 typ 0.05 0.15 0 7 0.08max figure 1 8 . 128 - pin tqfp package physical dimension detail of lead end 25/27
thcv226_rev.1.10_e copyright?201 5 thine electronics, inc . thine electronics, inc. s ecurity e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circui t diagrams described in this material are examples of the application which may not always apply to the cus tomer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. copying or disclosing to third parties the contents of t his material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. this product must not be used for applications that require extremely hi gh -reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine electronics, inc. (thine) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain sm all probability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product caus e any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product . except where mandated by applicable law or deemed necessary by thine based on the users request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the for eign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damage may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. 26/27
thine electronics, inc. security e thcv220_rev.2.20_e copyright?2 01 6 thine electronics, inc. 2 7/27

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